The quality of a clock signal tends to degrade as the signal travels down a transmission line due to attenuation, interference, noise, and a number of other factors. One method of compensating for this problem at the receiving end is by using a phase-locked loop (“PLL”) to synthesize a signal having the same frequency and wave form as the original clock signal. FIG. 1 illustrates a functional block diagram of a basic PLL. A phase comparator 10 produces a DC or low frequency signal having a voltage proportional to the phase difference between an input signal and an output signal (which also acts as the reference signal for the phase comparator 10). The DC or low frequency signal from the phase comparator 10 is filtered by a low frequency loop filter 12 and applied to the input of a voltage-controlled oscillator (“VCO”) 14. The VCO increases or decreases the frequency of the output signal based on the voltage of the signal from the phase comparator 10. The output signal is then fed back to the phase comparator 10 for phase comparison with the input signal. If the frequencies of the two signals are different, resulting in a phase difference, the phase comparator 10 adjusts the control signal voltage until the VCO 14 has increased or decreased the output signal frequency sufficiently to eliminate the phase difference. In this way, the output signal can be phase-locked with the input signal.
PLLs generally have narrow bandwidths and, therefore, are limited in the range of frequencies the PLLs can phase lock. A PLL designed for low frequency will not generally phase lock a high frequency signal, and vice versa. This makes the basic PLL unsuitable for use in applications where broad bandwidths are required.
One attempt to address this shortcoming is to provide the PLL with multiple frequency ranges such as in Cypress Semiconductor's programmable skew clock buffer (“PSCB”). This integrated circuit timing generator includes, among other functions, an internal PLL with three user-selectable VCO frequency ranges: 15-30, 25-50, and 40-80 MHz. A user may configure the PSCB VCO to oscillate in any one of the three ranges by setting the appropriate input pins. Furthermore, the output of the PSCB VCO may be divided by up to a factor of four by appropriate selection of internal dividers. Division of the VCO output allows the PSCB PLL to phase lock signals having frequencies as low as 3.75 MHz (15 MHz÷4=3.75 MHz) even though such frequencies are technically outside the lowest PSCB VCO frequency range. Data sheets and application notes for the PSCB may be obtained from Cypress Semiconductor's home page, http://www.cypress.com, and are incorporated herein by reference.
Although the multiple frequency ranges of the PSCB PLL allow it to phase lock either high or low frequencies, the bandwidth of each frequency range is still relatively narrow. In other words, once the PSCB is configured to operate in a particular frequency range, it is effectively dedicated to that frequency range and will be unsuitable for use in applications requiring different frequency ranges or broader bandwidths.